As the DRAM cell is scaled towards the 256 Mb DRAM and beyond, innovative cell concepts are needed to push the cell area to practical limits. One such concept is to place the trench storage capacitor partially under the cell's access device. Although cell structures using such concepts as the buried trench cell have been proposed in the past, these structures rely on expensive selective epi growth techniques to reduce the trench opening. Selective epi growth, however, typically has a very high defect density and therefore is generally considered to be unsuitable for DRAM applications.
Thus, a need has arisen for a DRAM cell structure that can take advantage of the area minimization benefits of prior art trench-under-access device techniques, while avoiding the drawbacks associated with selective epi growth.